1. Field of the Invention
This disclosure relates to non-volatile storage.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in personal navigation devices, cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
In both EEPROM and flash memory, a memory cell includes a transistor with a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate and channel regions are positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction of current between its source and drain is controlled by the level of charge on the floating gate. The memory cell may connected to a bit line to allow the conduction current to be sensed.
When programming a memory cell in an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique for Non-Volatile Memory;” U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory;” and U.S. Pat. No. 6,888,758, titled “Programming Non-Volatile Memory,” all three cited patents are incorporated herein by reference in their entirety.
In many cases, the program voltage is applied to the control gate as a series of pulses (referred to as programming pulses), with the magnitude of the pulses increasing at each pulse. Between programming pulses, a set of one or more verify operations are performed to determine whether the memory cell(s) being programmed have reached their target level. If a memory cell has reached its target level, programming stops for that memory cell. If a memory cell has not reached its target level, programming will continue for that memory cell.
Memory cells in some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state).
A multi-state memory device stores multiple bits of data per memory cell by identifying multiple distinct valid threshold voltage (Vt) distributions (or data states). Each distinct Vt distribution corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, a memory cell that stores two bits of data uses four valid Vt distributions. A memory cell that stores three bits of data uses eight valid Vt distributions.
One factor that affects the reading of memory cell's Vt is the channel potential of its neighbor memory cell (or cells). For example, if the neighbor's drain side channel potential is 0.4 volts, the apparent Vt of a memory cell may be different than if the neighbor's drain side channel potential is 0 volts.
Once a non-volatile storage element has been programmed, it is important that its programmed state can be read back with a high degree of reliability. However, differences in the neighbor's channel potential between when the memory cell was verified and later read can impact the apparent Vt of the memory cell. Hence, the memory cell might be read incorrectly.
One technique for reducing the differences between program verify and read conditions such as differences in channel potential is to sense only every other bit line during program verify and read. This keeps the neighbor's channel potential at 0V during both during program verify and read. However, by only reading every other bit line at a time, the time to verify and read may double. Because many program cycles may be needed, each with its own verify operations, doubling the number of verify operations for each program cycle can be detrimental to performance.